A quick update to a previous post that I made:
http://blog.edmondcote.com/2017/03/register-bundle-in-chisel.html. Here is how I now create a register (sequential storage element) of a bundle in Chisel3. The benefit is the elimination of the previously-necessary wire declaration.
val pageReg: Page = RegInit({
val page = Wire(new Page())
page.initialize()
page
})