Quick addition to the previous
post. This technique is useful when prototyping hardware. Use LFSRs to drive pins/ports such that no logic pruning occurs its cone of logic during synthesis.
final def prng(bundle: Bundle): Unit = {
bundle.elements.filter(_._2.dir == OUTPUT).foreach {
case (n, d) => {
val r = Module(new LFSR(d.getWidth))
when(true.B) {
d := r.io.y
} } } }
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