Showing posts with label RISC-V. Show all posts
Showing posts with label RISC-V. Show all posts

Friday, January 12, 2018

Mid-January Update

November was mostly about writing a grant proposal for DARPA.  It has been 110% technical work since then.  Beginning in February, I will shift to writing pretty PowerPoint slides for the company.   I should have a minimum viable prototype by then.

I worked on an experiment to build a continuous integration environment for the software assets of the RISC-V Foundation; learning Groovy and Gradle the process.  The prototype uses Jenkins2 for which I have been pleasantly surprised.  My previous experience was Jenkins 1.x.  I published source code for the prototype here.  I plan to volunteer some time to help coordinate some this activity.  It is a small <5%-of-week commitment.

I began to move parts of my internal wiki to GitHub gists.  I plan to add more over time.

Finally, I am accumulating notes on how to bootstrap RocketChip.  You can find the notes here. 

Also, compared to six months ago, I am beginning to feel very comfortable writing functional code using Scala.  I struggle a bit here and there (i.e., when recursion comes into play), but overall it is a positive experience.  If I had time, I would love to take an advanced class.  It would be interesting to re-learn data structures, algorithms through a functional lense.

Thursday, December 14, 2017

Debugging Spike with CLion/CMake

Another quick entry.  I released a template project on GitHub that allows you to build, run, and debug spike, the RISC-V ISA simulation, using CLion.

https://github.com/edcote/spike-cmake

Clone, import the template, and enjoy!


Monday, December 29, 2014

Registered for RISC-V Workshop

I registered for the first RISC-V Workshop and Bootcamp that is being put together by the ASPIRE lab at UC-Berkeley.

If I have been quiet on the blog, it is because I have been exploring the RISC-V architecture and the Chisel hardware construction language.

I agreed to present a poster. Stay tuned :)