Check if sbt compile works from the command line for your Chisel project ...
[plus]:~/gitrepos/plus/arbiterdemo$ sbt compile [info] Loading global plugins from /home/edc/.sbt/0.13/plugins [info] Loading project definition from /home/edc/gitrepos/plus/arbiterdemo/project [info] Set current project to memctrldemo (in build file:/home/edc/gitrepos/plus/arbiterdemo/) [info] Updating {file:/home/edc/gitrepos/plus/arbiterdemo/}arbiterdemo... [..] [info] Done updating. [info] Compiling 3 Scala sources to /home/edc/gitrepos/plus/arbiterdemo/target/scala-2.11/classes... [success] Total time: 4 s, completed May 3, 2017 8:26:36 PM
Use the default project settings ...
Right click on your class that contains call to chisel3.Driver.execute, hit Run ...
Right click on your class that contains call to chisel3.Driver.execute, hit Run ...
Follow up by checking that that Verilog code is generated as expected (yes)
Finally, try setting a breakpoint by right clicking to the left of the source window and hit shift-F9 to begin debug. I was 100% successfull following only these steps on IDEA 2017.1 with the project-specific IDEA settings (i.e. .idea/ diretory) wiped out prior.
Finally, try setting a breakpoint by right clicking to the left of the source window and hit shift-F9 to begin debug. I was 100% successfull following only these steps on IDEA 2017.1 with the project-specific IDEA settings (i.e. .idea/ diretory) wiped out prior.
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