Source code for M.Sc thesis (2007) released

I have uploaded the source code to my M.Sc thesis project.  The main reason why this is worth checking out is because of the use of SystemVerilog features which were used in the feature.  The features include packages, typedef, interfaces, modports, always_comb blocks, and a good amount of parameterization.  Considering most of this work was done in 2006-2007, I think its pretty impressive.

Please visit the following repository : https://bitbucket.org/ecote/system99/src

Early January Hack - Practical RISC-V Random Test Generation using Constraint Programming

As hinted in my previous blog post, here is the presentation I did for RISC-V workshop :



I will not release the test generator quite yet. The method I chose to input the problem to the constraint solver is too verbose.  I am already looking at an alternative solution using Python introspection and or-tools from Google.

I do have a patch for spike to allow the tool to be controlled from a different process.  I can release that if there is interest.

Mako templates for Verilog, now released

I cleaned up and published code I presented earlier this year on the use of Mako templates for Verilog.

Here is a link to the repository: https://bitbucket.org/ecote/vmako/overview

Update to SimpleMIPS to use elftools, improved tracing, and new instructions

In the spirit of the new year, I am publishing some code that I have laying around on my workstation.

SimpleMIPS is an existing Python-based instruction set simulator for MIPS.  I wrote some code to replace its roll-your-own ELF parser with code from elftools library, to add simple for instruction trace generation, and add support for handful of new instructions.

Here is a link to my the repository : https://bitbucket.org/ecote/miss/overview

Registered for RISC-V Workshop

I registered for the first RISC-V Workshop and Bootcamp that is being put together by the ASPIRE lab at UC-Berkeley.

If I have been quiet on the blog, it is because I have been exploring the RISC-V architecture and the Chisel hardware construction language.

I agreed to present a poster. Stay tuned :)