Wednesday, May 28, 2014

Wednesday Night Hack #1

This week, I began the development of basic a front end tool to wrap the functionality of the CAD tools bundled with my LatticeECP3 FPGA development board.  The packaged tools are Aldec-HDL, Synplify Pro, and Lattice Diamond (the FPGA implementation tool).  Active-HDL, by all respects, have a pretty solid GUI, but my preference is to maintain control from the command line.

Rather than implement a custom Makefile library or a traditional Perl script, I chose to develop an API using Python that a user could use to build up their own flow apps.  The idea is to replace configuration files or application-specific dynamic scripting languages with an actual scripting language.  This approach scales better over time.

The first step to this process is project management. We want the ability to manage groups of files.  I call these groups of files components.  Examples of components include RTL unit (Verilog module and its sub modules), UVC (Universal Verification Component), design IP library (RAM library, FPGA megafunctions), etc.

We also want the ability to establish "depends on" relationships between components.  Here is an example component definition written in Python


For a simple project consisting of three components. Top, RAM, and LED where top depends on RAM and LED and LED also depends on RAM.  The flist would need to resemble following.  The script below is able to produce this.  In fact, below is the actual output of the script.

# Component: ram

# Component: led
# Requires: ram

# Component: top
# Requires: led,ram

I achieve this functionality by implementing two classes in Python: Component and Go.  Here are some code snippets.  First, I build a tree data structure in process_requires function.  I traverse the tree in function get_flist using a simple recursive algorithm.

Here is a snippet of the source code.  There's no error checking, so YMMV.

class Component:
    """ Exposed to user """
    def add_file(self, file):

    """ Exposed to user """
    def add_option(self, option):

    """ Exposed to user """
    def add_require(self, require):

    def get_flist(self):
        flist = '#' * 80 + '\n' # 80 character comment line
        flist +=  '# Component: ' + self.get_name() + '\n'
        if self.requires:
            flist +=  '# Requires: '+','.join(self.requires)+'\n'
        if self.files:
            flist +=  '\n'.join(self.files) + '\n'
        if self.options:
            flist +=  '\n'.join(self.options) + '\n'
        return flist

class Go:
    """ Load all component under root_dir """
    def load_comps(self):
        for root,dirs,files in os.walk(self.root_dir):
            for f in files:
                if f == '':
                    c = Component()
                    self.component[c.get_name()] = c

    def process_requires(self,node):
        for require in node.requires:
            child_node = self.component[require]

    def init(self):

    def get_flist(self):
        self.visited = {}

    """ Traverse tree using recursive post-order search """
    def do_get_flist(self,node):
        for child in node.child_nodes:
            if not child.get_name() in self.visited:
        if not node.get_name() in self.visited:
           self.visited[node.get_name()] = 1 # mark visited

Wednesday, May 21, 2014

Back to Basics

I have been working in hardware design verification since I graduated from school.  It has been nearly 7 years now, time flies, I can hardly believe it.

Hardware design verification is an extremely exciting field.  The field requires knowledge spanning multiple disciplines: software development, hardware implementation, and (in my case) computer/graphics systems.

My job at Qualcomm is also extremely challenging, we are at the forefront of all the above.

At school, I wasn't interested so much in academics or research as I was building things.  I spent a substantial amount of time working on overly ambitious projects.

The best example of that, perhaps, was my digital VLSI circuits class where I spent more time playing with tools to generate GDS-II from RTL than focusing on the class assignment which was to design and layout a custom digital cell.

In my undergraduate computer graphics class, I went way beyond the defacto rendered-with-OpenGL textured cube or simple ray tracer. I wrote my own scene graph, associated rendering engine, and custom Python-based Blender3D export plugin.  Not only that, but I took it a step further and wrote some custom shaders in ARB assembly language.  This was before there were high-level shader languages.

Fast forward to grad school.  I had taken a keen interest in computer architecture.  The thought and opportunity to understand these systems from the ground up was (and still is) very exciting for me.

As you can imagine, I wasn't interested so much in research as I was in hacking.  I spent a substantial amount of time building my own multiprocessor system-on-a-chip from the ground up and prototyped it on an FPGA.

The final product was documented in my thesis and in two conference papers.  Granted, my contributions weren't ground breaking, but in retrospec, it was a very rewarding experience.

Over the past few years, I haven't tinkered so much. I worked. I lived. I got married. I am still learning about work-life balance. But, the bug to tinker is still in me.

This long winded rant to say that I have recently been researching FPGA prototype boards to purchase and settled on this one the other day.  Besides cost, I was motivated by the availability of Ethernet ports and PCIe connector.  I/O is an area of system design that I know next to nothing about.

I do not plan to make any commitments regarding my tinkering, but it is a part of me that I hope to resurrect.