Friday, March 24, 2017

Register a bundle in Chisel

I have been playing with more with Chisel lately.  An area I find lacking in the documentation is how to register a bundle (i.e. struct).  Most examples I have seen use simple registers with type UInt.

It took some trial and error, but here is an example that elaborates and synthesizes properly.

class DDR3Command extends Bundle {
  val casN = UInt(1.W)
  val rasN = UInt(1.W)
  val ba = UInt(3.W)

  // user function to specify defaults (sync reset)
  def defaults() = {
    casN := 1.U
    rasN := 1.U
    ba := 0.U

class MemoryController extends Module {
  val io = IO(new Bundle {
    val ddr3 = Output(new DDR3Command())

  // create a wire of the bundle and set it's default values (sync reset)
  val resetDDR3Cmd = Wire(new DDR3Command())

  val nextDDR3Cmd = Reg(new DDR3Command(), init=resetDDR3Cmd)

  // for example purposes, only update select fields
  when (true.B) { := 3.U
    nextDDR3Cmd.casN := 0.U
    //nextDDR3Cmd.rasN := 1.U

  io.ddr3 := nextDDR3Cmd

Friday, March 10, 2017

REX to Intel and proud of the team

I left REX Computing about 1 year ago for reasons I choose not to disclose publically.  What I will say is that I am proud of the team to have brought the design through final tapeout, board development and now bring up.  I'm looking forward to the final power & performance numbers and, hopefully, an announcement about the software stack.  Here's Thomas (smart guy, 2013 Thiel fellow) presenting the hardware at Standford.  It's not the best quality and they were hit by Murphy's Law during the demo.  I'll switch up the video when a better presentation becomes available.

I am at Intel now (have been for 1 year).  The team develops verification testbench collateral to support the functional verification of their Xeon-line of server CPUs (Xeon, Xeon PHI, Xeon-D, etc.).  In a nutshell, my role is to manage a portion of a distributed "software" team (and virtual team) within a large organization that works on scrum-like sprints.  I am being challenged in different ways than previous - thus I am growing and grateful.

No official comment yet on the previous post.

Wednesday, December 23, 2015

Belated Update and Happy Holidays!

It's been rather quiet here, for good reason.

I took a new job last Fall!

As Director of Engineering, I am leading all aspects of hardware development at REX.

My responsibilities, so far, have included: recruiting and staffing of the hardware team, negotiations with CAD, foundry, and IP partners, leading chip architecture, development of front- and back- end CAD flows, RTL design and static timing analysis, and of course, covering all aspects of verification.

REX is a startup in the true sense of the word and the work is highly rewarding.

As the team grows, I will slowly let go of day-to-day RTL coding, CAD flows, and block-level verification and spend more time doing system modeling and hardware/software co-verification.

It's been a great 2015.  Wishing everyone the most joyous holidays and a happy new year!

Tuesday, July 14, 2015

Weeknight Hack #17 - Keeping a Pulse

No rocket science tonight.  Just some easy hacking.

I finally root caused the Z-wave device interview failure that I was facing.  The reason for failure was defective daughter board from  It was a hunch that I had a few weeks back.  On a whim, I obtained a replacement board and only got around to trying it tonight.

Also, I resolved networking issues on my Raspberry Pi.  My home router (a very basic one that I've had since college) doesn't support port forwarding to DHCP clients.  I will need the port forwarding to control my HAN from outside the home.  The workaround was setup the Pi to use a static IP.  The router supports port forwarding to static IPs.

It is work in progress to schedule in a weeknight to work on off-the-clock projects.  I hope to resolve this soon (requires coordinating with the wife).  The other issue has been lack of A/C in my office / workshop (garage actually!).