What's Been Up?

I can finally broadcast what I've been working on since I shut down my company at the end of 2018. I have been at Google working on:

https://blog.google/products/pixel/introducing-google-tensor/

For Tensor GS101, I primarily worked behind the scenes as lead, then manager, of a design verification CAD team. I later switched to a design verification lead role for YouTube's Argos ASIC, specifically on the video codec IP written using C++ and synthesized using HLS. Following some reshuffling, I continue doing the same, but for something different, still 100% confidential. Hope to talk about it soon!

Register a bundle in Chisel3

A quick update to a previous post that I made: http://blog.edmondcote.com/2017/03/register-bundle-in-chisel.html.  Here is how I now create a register (sequential storage element) of a bundle in Chisel3.  The benefit is the elimination of the previously-necessary wire declaration.

val pageReg: Page = RegInit({
  val page = Wire(new Page())
  page.initialize()
  page
})