Thursday, June 12, 2014

Planning Ahead - SystemVerilog-Design and Networking Hardware

Chapter 10 of SystemVerilog for Design showcases the design of a Asynchronous Transfer Mode (ATM) user-to-network interface (UNI) and forwarding node.

I have no idea what that means.  Besides configuring home routers and configuring Windows / Linux PC to access them, I have next-to-no background in low-level computer networking.

The chapter also claims to summarize the SystemVerilog-Design concepts presented in the book.

I think it will be an interesting challenge to review the design presented in the book and attempt to implement it on my FPGA device.  It will be a good refresher for SystemVerilog-Design and I will learn a little something about networking hardware design.

I am hopeful that today's (2014) bundled synthesis tools are up for the challenge.