Quick post. I spent some time yesterday/today hacking at the TileLink2 implementation in RocketChip.
(As a matter of coincidence, SiFive recently released a draft spec of the protocol.)
My preferred method of learning is first to understand the engineer's original intent before enhancing or leveraging code. This means taking things apart.
The most difficult aspect in getting something up was understanding the inner workings of SystemBus class. I kept hitting run time assertions and it was helpful to manually sketch out the connections between the TL objects:
Here is a summary of my findings.
I identified the minimal set of configuration knobs for this experiment.
This is the system itself. It extends BaseComplex. Not RocketComplex.
This should be familiar. It is your top level Chisel3 module.
Here are the important parts of the system generator. This will generate your firrtl and verilog output.
Finally, one should never forget unit testing!