Sunday, May 8, 2011

Vim Setup for SystemVerilog

It took some time and effort on my part to really become comfortable with using Vim.  Eventually, I became so productive with using the text editor that it became unnecessary to use anything besides it.

The two features that got me hooked to the text editor are the ability the select and manipulate columns in visual block mode and the large number of third-party plugins available.  My primary use for Vim is for programming in SystemVerilog.  I have found that the following plugins are extremely useful:
The typical use of the % key in Vim is to move the cursor between matching curly braces.  I have a seen a number of SystemVerilog users adopt the following convention to make use of the feature.  It is a cumbersome practice that is entirely avoidable.

if (condition) begin // {
end // }

When configured correctly, match_it.vim allows the % key to be configured to match more than just single characters.  In the context of SystemVerilog, we can enable the user to move the cursor between Verilog-style statements that define blocks of code (e.g. begin/end, class/endclass, package/endpackage, etc.)

Configuring the plugin is pretty straightforward.  I started with the configuration posted at and made some minor tweaks (make sure to use the tick character ', not `, ‘, or ’ when defining b:match_words).

filetype plugin on

source ~/.vim/plugin/matchit.vim

if exists('loaded_matchit')
let b:match_ignorecase=0
let b:match_words=
  \ '\<begin\>:\<end\>,' .
  \ '\<if\>:\<else\>,' .
  \ '\<module\>:\<endmodule\>,' .
  \ '\<class\>:\<endclass\>,' .
  \ '\<program\>:\<endprogram\>,' .
  \ '\<clocking\>:\<endclocking\>,' .
  \ '\<property\>:\<endproperty\>,' .
  \ '\<sequence\>:\<endsequence\>,' .
  \ '\<package\>:\<endpackage\>,' .
  \ '\<covergroup\>:\<endgroup\>,' .
  \ '\<primitive\>:\<endprimitive\>,' .

  \ '\<specify\>:\<endspecify\>,' .
  \ '\<generate\>:\<endgenerate\>,' .
  \ '\<interface\>:\<endinterface\>,' .
  \ '\<function\>:\<endfunction\>,' .
  \ '\<task\>:\<endtask\>,' .
  \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
  \ '\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,' .
  \ '`ifdef\>:`else\>:`endif\>,'

I only use the syntax plugin included in the verilog_systemverilog.vim package because I am disciplined enough to do a better job than the tool can.  The automation identation functionality gets in the way for me.  My filetype configuration for SystemVerilog files is as follows:

syntax on

autocmd BufRead,BufNewFile *.v,*.vh setfiletype verilog
autocmd BufRead,BufNewFile *.v,*.vh set expandtab tabstop=4 softtabstop=2 shiftwidth=2

autocmd BufRead,BufNewFile *.sv,*.svi set filetype=verilog_systemverilog
autocmd BufRead,BufNewFile *.sv,*.svi set expandtab tabstop=4 softtabstop=2 shiftwidth=2

I prefer spaces to tabs for the simple reason that the only way to align a a block of code idented with tabs is to use spaces, so why use tabs to begin with?  The only exception that I have found to the rule is for assembly languages and makefiles (because they require the use of the tab character).  Opinions vary widely on the subject, but the most important take away is to be aware of how the original author of the file that you are editing has chosen to ident their code and to not deviate from it.  To view the type of whitespace used for the file being edited, you can set these options in your .vimrc:

set listchars=eol:$,tab:\>\ ,trail:.,extends:>,precedes:<
set list   " to turn on (use :set nolist to turn off)

The last plugin that I have decided to blog about is vcscommand.vim (not to be confused with the simulator from Synopsys).  This plugin script is an excellent front end to CVS, SVN, and other source code control systems.  The feature that I use the most is command :VCSVimDiff to display differences between the most recent version of the file and the checked-in version of the file.  I map this command to key F12.  There are other options for file check in but I'll typically use the command line to do so.

map <F12> :VCSVimDiff<CR> " map F12


  1. can you please give me clear instructions on how to enable syntax highlighting for SystemVerilog in VIM editor ? What file to copy paste and where to ??
    I have a .vimrc file in my $HOME , but no directory as .vim/ ..

  2. @Niketh: The answer to your question is outside of the scope of this article. You can find more information about how to configure Vim using your friend Google.